This relates to integrated circuits and more particularly, to programmable integrated circuits.
Programmable integrated circuits are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design (CAD) tools to design a custom logic circuit. When the design process is complete, the computer-aided design tools generate configuration data. The configuration data is loaded into memory elements to configure the devices to perform the functions of the custom logic circuit.
Memory elements are often formed using random-access-memory (RAM) cells. Because the RAM cells are loaded with configuration data during device programming, the RAM cells are sometimes referred to as configuration memory or configuration random-access-memory cells (CRAM). During normal operation of a programmable device, loaded CRAM cells produce static output signals that are applied to the gates of transistors (e.g., pass transistors). The CRAM output signals turn some transistors on and turn other transistors off. This selective activation of certain transistors on the programmable device customizes the operation of the programmable device so that the programmable device performs its intended function.
Each memory cell typically includes a bistable storage circuit (i.e., a storage circuit that includes two cross-coupled inverters) that is coupled to data lines via address transistors. The address transistors are controlled by address signals. During read and write operations, the address signals may be selectively asserted to access a subset of memory cells. In a 14 nanometer (nm) process, the bistable storage portion may be powered using a nominal voltage supply of 0.90 V and a ground voltage supply of 0 V.
In an effort to improve read/write margin and reduce leakage in the memory cells, the address signals may be driven from an overdrive voltage of 1.1 V to a negative voltage of −0.1 V. In certain applications, the address signals to the memory cells have to be gated using gating logic. The gating logic is implemented using thin-gate devices, which can only withstand a maximum voltage swing of 1.13 V in the 14 nm process. However, driving the gating logic between 1.1 V and −0.1 V results in an overall voltage swing of 1.2 V (1.1 minus −0.1), which violates the maximum tolerable voltage swing. This violation could result in undesirable device reliability issues and could cause breakdown and defects in the memory cells.
It is within this context that the embodiments described herein arise.